1. Field of the Invention
The present invention relates generally to a semiconductor memory device, and to a circuit technique that ensures high-speed readout even with a miniaturized device at low voltages.
2. Related Background Art
FIG. 9 is a circuit diagram illustrating a configuration of a contact-type mask ROM as a conventional semiconductor memory device. The contact-type mask ROM is configured so that the connection and the disconnection between a drain of a memory cell transistor and a bit line correspond to xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d as ROM data, respectively.
In FIG. 9, the conventional semiconductor memory device is composed of a memory cell array 1, a row decoder 2, a precharge transistor 3, a readout circuit 4, a bit line selection circuit 14, and a column decoder 15.
The memory cell array 1 includes memory cells M(i,j) (i=1 to m, j=1 to n) that are arrayed in matrix of m rowsxc3x97n columns. Gates of the memory cells M(i,j) are connected with word lines Wi (i=1 to m), respectively. Sources thereof are connected to a ground potential, and drains thereof are connected to bit lines BLj (j=1 to n), respectively, when the memory cell data is xe2x80x9c0xe2x80x9d, whereas they are floated when the memory cell data is xe2x80x9c1xe2x80x9d.
The row decoder 2 is supplied with row addresses AR1 to ARy and a precharge signal PCLK as inputs thereto. The row decoder 2 makes all the word lines Wi (i=1 to m) unselected when the precharge signal PCLK is at a logic xe2x80x9cLxe2x80x9d level, and it selects the word lines Wi (i=1 to m) corresponding to inputs of the row addresses AR1 to ARy when the precharge signal PCLK is at a logic xe2x80x9cHxe2x80x9d level. In this conventional example, the selected word lines Wi have the xe2x80x9cHxe2x80x9d level, and the other lines Wi have the xe2x80x9cLxe2x80x9d level.
The precharge transistor 3 is a P-type MOS transistor whose source is connected with a power source potential, whose gate is fed with the precharge signal PCLK, and whose drain is connected to a connection DINA that is connected with the bit line selection circuit 14.
The readout circuit 4 amplifies a signal at the connection DINA connected with the bit line selection circuit 14, and outputs memory data to an output terminal DOUT. The output terminal DOUT outputs data of xe2x80x9c1xe2x80x9d when the connection DINA has the xe2x80x9cHxe2x80x9d level, and outputs data of xe2x80x9c0xe2x80x9d when the connection DINA has the xe2x80x9cLxe2x80x9d level.
The bit line selection circuit 14 is composed of N-type MOS transistors QNj (j=1 to n) whose sources are connected to bit lines BLj (j=1 to n), respectively, whose gates are connected to a bit line selection signal Cj (j=1 to n), respectively, and whose drains are connected to the connection DINA, and P-type MOS transistors QPj (j=1 to n) whose drains are connected to bit lines BLj (j=1 to n), respectively, whose sources are connected to bit line selection signals /Cj (j=1 to n), respectively, and whose sources are connected to a connection DINA connecting the drain of the precharge transistor 3 and the readout circuit 4.
The column decoder 15 selects bit line selection signals Cj (j=1 to n) and /Cj (j=1 to n) according to each of column addresses AC1 to ACx supplied thereto. In this conventional example, the selected Cj (j=1 to n) has the xe2x80x9cHxe2x80x9d level, while the other Cj (j=1 to n) has the xe2x80x9cLxe2x80x9d level. The selected /Cj (j=1 to n) has the xe2x80x9cLxe2x80x9d level, while the other /Cj (j=1 to n) has the xe2x80x9cHxe2x80x9d level.
An operation of reading out data from a memory cell M(i,j) in the semiconductor memory device thus configured is described with reference to a timing chart of FIG. 10, taking an operation of reading out data from a memory cell M(2,2) as an example. In this conventional example, in the initial state, the word lines Wi, the bit line selection signals Cj and /Cj, the bit lines BLj, the connection DINA, and the output terminal DOUT have a ground potential.
In FIG. 10, while the precharge signal PCLK is at the xe2x80x9cLxe2x80x9d level, the row addresses AR1 to ARy make transition to addresses for selecting the word line W2 and are inputted to the row decoder 2, and the column addresses AC1 to ACx make transition to addresses for selecting the bit line BL2 and are inputted to the column decoder 15.
Thus, the row decoder 2 makes all the word lines Wi (i=1 to m) have the xe2x80x9cLxe2x80x9d level so as to cause the memory cells M(i,j) whose gate are connected with the word lines Wi to be in the non-conducting state. The column decoder 15 causes the bit line selection signals C2 and /C2 corresponding to the second column to make transition to the xe2x80x9cHxe2x80x9d level and the xe2x80x9cLxe2x80x9d level, respectively, and causes the other bit line selection signals Cj (j=1, 3, . . . n) and /Cj (j=1, 3, . . . n) to make transition to the xe2x80x9cLxe2x80x9d level and to the xe2x80x9cHxe2x80x9d level, respectively. This causes only the N-type MOS transistor QN2 and the P-type MOS transistor QP2 to make transition to the conducting state, and so as to cause the other N-type MOS transistors QNj (j=1, 3, . . . n) and P-type MOS transistors QPj (j=1, 3, . . . , n) to make transition to the non-conducting state.
Since the precharge signal PCLK is at the xe2x80x9cLxe2x80x9d level, the precharge transistor 3 is in the conducting state, and the connection DINA that is connected with the bit line selection circuit 14 and the bit line BL2 connected with the N-type MOS transistor QN2 and the P-type MOS transistor QP2 that are in a state of being conducted are charged so as to have a power source potential over a period of time t0c. 
Subsequently, since the precharge signal PCLK makes transition to the xe2x80x9cHxe2x80x9d level, the row decoder 2 causes the word line W2 to make transition to the xe2x80x9cHxe2x80x9d level, and causes the other word lines Wi (i=1, 3, . . . , m) to remain at the xe2x80x9cLxe2x80x9d level, so that the memory cells M(2,j) (j=1 to n) whose gates are connected with the word line W2 make transition to the conducting state.
Thereafter, when the memory cell M(2,2) is not connected with the bit line BL2, that is, the ROM data is xe2x80x9c1xe2x80x9d, charges accumulated in the connection DINA and the bit line BL2 are not discharged, and the readout circuit 4 outputs data of xe2x80x9c1xe2x80x9d to the output terminal DOUT. On the other hand, when the memory cell M(2,2) is connected with the bit line BL2, that is, the ROM data is xe2x80x9c0xe2x80x9d, charges accumulated in the connection DINA and the bit line BL2 are discharged, so that the readout circuit 4 outputs data of xe2x80x9c0xe2x80x9d to the output terminal DOUT after a period of time t0r. 
This conventional semiconductor memory device has the following drawbacks.
Since several hundreds to several thousands of memory cell transistors are connected with a bit line in the semiconductor memory device, there has been a drawback in that it takes a long time to charge a bit line with a large capacity to the power source potential.
Besides, since the bit lines are precharged via the transistors composing the bit line selection circuit 14, in order to shorten the precharge time, a gate width of the precharge transistor 3 and gate widths of the transistors composing the bit line selection circuit 14 have to be widened so as to lower ON resistances of the transistors of the both.
However, when the gate widths of the transistors composing the bit line selection circuit 14 are widened, gate capacitances thereof increase, thereby causing load capacitances of bit line selection signals supplied to the gates to increase. This results in an increase in the load capacitances charged by the precharge transistor 3, thereby causing the time required for the bit line selection to be prolonged.
Besides, since the gate width of the memory cell transistor is reduced to be as small as possible with a view to decreasing the space occupied by the memory cell transistor, there also has been a drawback in that the ON resistance becomes high and that a time required for discharging charges accumulated up to the power source potential becomes long.
Furthermore, in the case where intervals between bit lines that are arranged parallel with each other by mask layout are minimized to a limit of the micromachining technology, there has been a drawback in that capacitances between the bit lines increase, thereby causing malfunctions due to this to occur.
The following description will depict the malfunctions stemming from the increase in the line capacitances between the bit lines, while referring to the circuit diagram of FIG. 9 and the timing chart of FIG. 11.
In FIG. 9, assume that the memory cells M(2,1) and M(2,3) are connected with the bit lines BL1 and BL3, respectively, and the other memory cells M(i,j) are not connected with the bit lines BLj.
(1) In FIG. 11, in the first period, while the precharge signal PCLK is at the xe2x80x9cLxe2x80x9d level, the row addresses AR1 to ARy make transition to addresses for selecting the word line W1 and are fed to the row decoder 2. On the other hand, the column addresses AC1 to ACx make transition to addresses for selecting the bit line BL1 and are fed to the column decoder 15.
First of all, the row decoder 2 causes all the word lines Wi (i=1 to m) to make transition to the xe2x80x9cLxe2x80x9d level, thereby causing the memory cells M(i,j) whose gates are connected with the word lines Wi (i=1 to m) to make transition to the non-conducting state. The column decoder 15 causes the bit line selection signals C1 and /C1 corresponding to the first column to make transition to the xe2x80x9cHxe2x80x9d level and the xe2x80x9cLxe2x80x9d level, respectively, while causing the other bit line selection signals Cj and /Cj (j=2 to n) to make transition to the xe2x80x9cLxe2x80x9d level and the xe2x80x9cHxe2x80x9d level, respectively, thereby causing the N-type MOS transistor QN1 and the P-type MOS transistor QP1 to make transition to the conducting state, and causing the other N-type MOS transistors QNj and P-type MOS transistors QPj (j=2 to n) to make transition to the non-conducting state.
Here, since the precharge signal PCLK is at the xe2x80x9cLxe2x80x9d level, the precharge transistor 3 makes transition to the conducting state. Therefore, the connection DINA connected with the bit line selection circuit 14, and the bit line BL1 connected with the N-type MOS transistor QN1 and the P-type MOS transistor QP1 that are in the conducting state, are charged.
Then, as the precharge signal PCLK makes transition to the xe2x80x9cHxe2x80x9d level, the row decoder 2 causes the word line W1 to make transition to the xe2x80x9cHxe2x80x9d level, and causes the other word lines Wi (i=2 to m) to remain at the xe2x80x9cLxe2x80x9d level, thereby causing the memory cells M(1,j) (j=1 to n) whose gates are connected with the word line W1 to make transition to the conducting state. Charges accumulated in the bit line BL1, however, are not discharged since the memory cell M(1,1) is not connected with the bit line BL1, and the potential of the bit line BL1 is maintained during the first period.
(2) Next, in the second period, while the precharge signal PCLK is at the xe2x80x9cLxe2x80x9d level, the row addresses AR1 to ARy maintain the address for selecting the word line WI and are fed to the row decoder 2. On the other hand, the column addresses AC1 to ACx make transition to addresses for selecting the bit line BL3 and are fed to the column decoder 15.
First of all, the row decoder 2 causes all the word lines Wi (=1 to m) to make transition to the xe2x80x9cLxe2x80x9d level, thereby causing the memory cells M(i,j) whose gates are connected with the word lines Wi (i=1 to m) to make transition to the non-conducting state, and the column decoder 15 causes the bit line selection signals C3 and /C3 corresponding to the third column to make transition to the xe2x80x9cHxe2x80x9d level and the xe2x80x9cLxe2x80x9d level, respectively. This causes the other bit line selection signals Cj and /Cj (j=1, 2, 4, . . . , n) to make transition to the xe2x80x9cLxe2x80x9d level and the xe2x80x9cHxe2x80x9d level, respectively. This causes the N-type MOS transistor QN3 and the P-type MOS transistor QP3 to make transition to the conducting state, and causes the other N-type MOS transistors QNj and P-type MOS transistors QPj (j=1, 2, 4, . . . , n) to make transition to the non-conducting state.
Here, since the precharge signal PCLK is at the xe2x80x9cLxe2x80x9d level, the precharge transistor 3 makes transition to the conducting state, and therefore, the connection DINA connected with the bit line selection circuit 14, and the bit line BL3 connected with the N-type MOS transistor QN3 and the P-type MOS transistor QP3 that are in the conducting state, are charged.
Then, as the precharge signal PCLK makes transition to the xe2x80x9cHxe2x80x9d level, the row decoder 2 causes the word line W1 to make transition to the xe2x80x9cHxe2x80x9d level, and causes the other word lines Wi (i=2 to m) to remain at the xe2x80x9cLxe2x80x9d level, thereby causing the memory cells M(1,j) (j=1 to n) whose gates are connected with the word line W1 to make transition to the conducting state. Charges accumulated in the bit line BL3, however, are not discharged since the memory cell M(1,3) is not connected with the bit line BL1, and the potential of the bit line BL3 is maintained during the second period. Besides, BL1 that was charged during the first period maintains its potential during the second period, since the charges are not discharged.
(3) Next, in the third period, while the precharge signal PCLK is at the xe2x80x9cLxe2x80x9d level, the row addresses AR1 to ARy makes transition to an address for selecting the word line W2 and are fed to the row decoder 2. On the other hand, the column addresses AC1 to ACx make transition to addresses for selecting the bit line BL2 and are fed to the column decoder 15.
First of all, the row decoder 2 causes all the word lines Wi (i=1 to m) to make transition to the xe2x80x9cLxe2x80x9d level, thereby causing the memory cells M(i,j) whose gates are connected with the word lines Wi (i=1 to m) to make transition to the non-conducting state, and the column decoder 15 causes the bit line selection signals C2 and /C2 corresponding to the second column to make transition to the xe2x80x9cHxe2x80x9d level and the xe2x80x9cLxe2x80x9d level, respectively, while causing the other bit line selection signals Cj and /Cj (j=1, 3, . . . , n) to make transition to the xe2x80x9cLxe2x80x9d level and the xe2x80x9cHxe2x80x9d level, respectively. This causes the N-type MOS transistor QN2 and the P-type MOS transistor QP2 to make transition to the conducting state, and causes the other N-type MOS transistors QNj and P-type MOS transistors QPj (j=1, 3, . . . , n) to make transition to the non-conducting state.
Here, since the precharge signal PCLK is at the xe2x80x9cLxe2x80x9d level, the precharge transistor 3 makes transition to the conducting state, and therefore, the connection DINA connected with the bit line selection circuit 14, and the bit line BL2 connected with the N-type MOS transistor QN2 and the P-type MOS transistor QP2 that are in the conducting state, are charged.
Then, as the precharge signal PCLK makes transition to the xe2x80x9cHxe2x80x9d level, the row decoder 2 causes the word line W2 to make transition to the xe2x80x9cHxe2x80x9d level, and causes the other word lines Wi (i=1, 3, . . . m) to remain at the xe2x80x9cLxe2x80x9d level, thereby causing the memory cells M(2,j) (j=1 to n) whose gates are connected with the word line W2 to make transition to the conducting state.
Here, as assumed above, the memory cells M(2,1) and M(2,3) are connected with the bit lines BL1 and BL3, respectively, and hence, the charges accumulated in the bit lines BL1 and BL3 in the first and second periods, respectively, are discharged. Accordingly, from the bit line BL2 that is provided between the bit lines BL1 and BL3 and that has been charged while the precharge signal PCLK is at the xe2x80x9cLxe2x80x9d level in the third period, charges are discharged via the line capacities between the bit lines BL1 and BL2 and between the bit lines BL2 and BL3. This causes the potential of the bit line BL2 to decrease. As a result, the potential of the connection DINA decreases also, from the xe2x80x9cHxe2x80x9d level to the xe2x80x9cLxe2x80x9d level, thereby causing the readout circuit 4 to mistakenly output xe2x80x9c0xe2x80x9d to the output terminal DOUT, which is different from the data xe2x80x9c1xe2x80x9d stored in the memory cell M(2,2). This phenomenon is more noticeable as the line capacitance between the bit lines increases.
The present invention is intended to solve the aforementioned problems of the conventional semiconductor memory device, and it is an object of the present invention to provide a semiconductor memory device that is capable of reading out data at a higher speed and that does not undergo a malfunction even in the case where bit line intervals are minimized so as to reduce the chip area.
To achieve the foregoing object, a semiconductor memory device of the present invention is a semiconductor memory device that reads out data from memory cells provided in a matrix according to address signals supplied from outside. The semiconductor memory device includes a bit line selection circuit including a plurality of first transistors for selecting a plurality of bit lines, respectively, according to a plurality of column selection signals that are generated based on the address signals, and a bit line charging circuit including a plurality of second transistors for charging the plurality of bit lines, respectively.
In this semiconductor memory device, the plurality of first transistors and the plurality of second transistors preferably are N-type MOS transistors. Each of the plurality of first transistors preferably has a gate, a source, and a drain so that the plurality of column selection signals are supplied to the gates, respectively, the plurality of bit lines are connected with the sources, respectively, and a precharge transistor for commonly charging the plurality of bit lines and a readout circuit for outputting data from the memory cells are connected commonly with the drains. Each of the plurality of second transistors preferably has a gate, a source, and a drain so that a bit line precharge signal that is supplied from outside is supplied commonly to the gates, a power source potential is supplied to the sources, and the plurality of bit lines are connected with the drains, respectively.
Alternatively, the plurality of first transistors and the plurality of second transistors preferably are N-type MOS transistors. Each of the plurality of first transistors preferably has a gate, a source, and a drain so that the plurality of column selection signals are supplied to the gates, respectively, the plurality of bit lines are connected with the sources, respectively, and a precharge transistor for commonly charging the plurality of bit lines and a readout circuit for outputting data from the memory cells are connected commonly with the drains. Each of the plurality of second transistors preferably has a gate, a source, and a drain so that a plurality of first selection signals are supplied to the gates, respectively, a power source potential is supplied to the sources, and the plurality of bit lines are connected with the drains, respectively.
Furthermore, the semiconductor memory device preferably further includes a bit line grounding circuit that includes a plurality of third transistors for connecting the plurality of bit lines with a ground potential, respectively. The plurality of third transistors preferably are N-type MOS transistors, and each of the N-type MOS transistors has a gate, a source, and a drain so that a plurality of second selection signals having logic states opposite to those of the plurality of column selection signals, respectively, are supplied to the gates, respectively, the sources are connected with a ground potential, and the drains are connected with the plurality of bit lines, respectively.
In this case, the plurality of first selection signals preferably are generated based on the plurality of second selection signals so as to have a delay of a predetermined time relative to the plurality of second selection signals.
Alternatively, the plurality of first selection signals preferably are generated so that only the bit line selected according to the address signals is precharged.
According to the foregoing configuration, in addition to the precharging operation common to the bit lines, a precharging operation is carried out by the second transistors that are provided for the bit lines, respectively. Therefore, the charging time during the bit line precharging operation and the discharging time during the memory cell data reading-out operation can be shortened, whereby data can be read out at a higher speed. Besides, by grounding adjacent bit lines that are not involved in the precharging or reading-out operation so that they have a ground potential, it is possible to eliminate a malfunction due to an increase in line capacitances between the bit lines, even if the bit line intervals are reduced to a minimum level to decrease the chip area.